View XR16L784_5629773.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? uarttechsupport@exar.com ? ? ? ? XR16L784 high performance 5v and 3.3v quad uart december 2001 rev.1.0.2 general description the XR16L784 1 (784) is a quad universal asynchro- nous receiver and transmitter (uart). the device is designed for high bandwidth requirement in commu- nication systems. the global interrupt source register provides a complete interrupt status indication for all 4 channels to speed up interrupt parsing. each uart has its own 16c550 compatible set of configuration registers, transmit and receive fifos of 64 bytes, ful- ly programmable transmit and receive fifo level trig- gers, transmit and receive fifo level counters, auto- matic rts/cts or dtr/dsr hardware flow control with programmable hysteresis, automatic software (xon/xoff) flow control, irda (infrared data associa- tion) encoder/decoder, and a 16-bit general purpose timer/counter. n ote : 1 covered by u.s. patents #5,649,122 and #5,832,205 applications ? remote access servers ? ethernet network to serial ports ? network management ? factory automation and process control ? point-of-sale systems ? multi-port rs-232/rs-422/rs-485 cards new features ? 5v and 3.3v operation with 5v tolerant inputs ? 8-bit intel or motorola data bus interface ? single open drain interrupt output for all 4 channels ? global interrupt source registers for all channels ? 5g (fifth generation) flat register set ? each uart is independently controlled with: ? 16c550 compatible registers ? 64-byte transmit and receive fifos ? transmit and receive fifo level counters ? programmable tx and rx fifo trigger levels ? automatic rts/cts or dtr/dsr flow control ? selectable rts flow control hysteresis ? automatic xon/xoff software flow control ? automatic rs485 half-duplex control output with 16 selectable turn-around delay ? infrared (irda 1.1) data encoder/decoder ? programmable data rate with prescaler ? up to 3.12 (16x) and 6.25 (8x) mbps data rate ? a general purpose 16-bit timer/counter ? sleep mode with automatic wake-up indicator ? 64-pin tqfp package (10x10x1.4 mm) f igure 1. b lock d iagram tmrck device configuration registers xtal1 xtal2 crystal osc/buffer tx0, rx0, dtr0#, dsr0#, rts0#, cts0#, cd0#, ri0# intel or motorola data bus interface tx3, rx3, dtr3#, dsr3#, rts3#, cts3#, cd3#, ri3# uart channel 3 uart channel 2 uart channel 1 16-bit timer/counter uart channel 0 64 byte tx fifo 64 byte rx fifo brg ir endec tx & rx uart regs 5v or 3.3v vcc gnd *all inputs are 5v tolerant 784blk rst# 16/68# enir a7:a0 ior# iow# cs# int# d7:d0
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 2 f igure 2. p in o ut a ssignment XR16L784 64-tqfp tx1 dtr1# rts1# ri1# cd1# dsr1# cts1# rx1 tx2 dtr2# rts2# ri2# cd2# dsr2# cts2# rx2 rx0 cts0# dsr0# cd0# ri0# rts0# dtr0# tx0 vcc gnd xtal1 xtal2 2 4567 9 8 3 1101113 12 14 15 16 34 33 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 64 63 62 61 60 59 58 57 55 56 54 53 52 51 31 32 17 18 19 20 21 22 23 24 26 25 27 28 29 30 enir tmrck vcc gnd cd3# dsr3# cts3# rx3 tx3 dtr3# rts3# ri3# rst# 16/68# d7 d6 int# cs# a0 a1 a2 a3 a4 a5 a6 a7 ior# iow# vcc gnd d0 d1 d2 d3 d4 d5 ordering information p art n umber p ackage o perating t emperature r angr XR16L784cv 64-tqfp (10 x 10 x 1.4mm) 0c to +70c XR16L784iv 64-tqfp (10 x 10 x 1.4mm) -40c to +85c
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 3 pin descriptions pin description n ame p in #t ype d escription data bus interface a7-a0 6-1,64,63 i address data lines [7:0]. a0:a3 selects individual uarts 16 configuration registers, a4:a6 selects uart channel 0 to3, and a7 selects the global device configuration registers d7:d0 18-11 io data bus lines (7:0] (bidirectional). ior# 7 i when 16/68# pin is at logic 1, it selects intel bus interface and this input is read strobe (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [a7:a0], puts it on the data bus to allow the host processor to read it on the leading edge. when 16/68# pin is at logic 0, it selects motorola bus interface and this input should be connected to vcc. iow# (r/w#) 8i when 16/68# pin is at logic 1, it selects intel bus interface and this input becomes write strobe (active low). the falling edge instigates the internal write cycle and the leading edge transfers the data byte on the data bus to an internal register pointed by the address lines. when 16/68# pin is at logic 0, it selects motorola bus interface and this input becomes read (logic 1) and write (logic 0) signal. cs# 62 i when 16/68# pin is at logic 1, this input is chip select (active low) to enable the XR16L784 device. when 16/68# pin is at logic 0, this input becomes the read and write strobe (active low) for the motorola bus interface. int# 61 od global interrupt output from XR16L784 (open drain, active low). this output requires an external pull-up resistor (47k-100k ohms) to operate properly. it may be shared with other devices in the system to form a single interrupt line to the host processor and have the software driver polls each device for the interrupt status. modem or serial i/o interface tx0 53 o uart channel 0 transmit data or infrared transmit data. rx0 60 i uart channel 0 receive data or infrared receive data. normal rxd input idles at logic 1 condition. the infrared pulses can be inverted internally prior to the decoder by fctr[4]. rts0# 55 o uart channel 0 request to send or general purpose output (active low). this port must be asserted prior using for one of two functions: 1) auto rts flow control, see efr bit-6, mcr bits-1 & 2, fctr bits 0-3 and ier bit-6 2) auto rs485 half-duplex direction control, see fctr bit-5, mcr bit-2 and msr bits 4-7. cts0# 59 i uart channel 0 clear to send or general purpose input (active low). it can be used for auto cts flow control, see efr bit-7, mcr bit-2 and ier bit-7. dtr0# 54 o uart channel 0 data terminal ready or general purpose output (active low). this port must be asserted prior using for one of two functions: 1) auto dtr flow control, see efr bit-6, fctr bits-0 to 3, mcr bits-0 & 2, and ier bit-6 2) auto rs485 half-duplex direction control, see fctr bit-5, mcr bit-2 and msr bit 4-7.
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 4 dsr0# 58 i uart channel 0 data set ready or general purpose input (active low). it can be used for auto dsr flow control, see efr bit-7, mcr bit-2 and ier bit-7. cd0# 57 i uart channel 0 carrier detect or general purpose input (active low). ri0# 56 i uart channel 0 ring indicator or general purpose input (active low). tx1 48 o uart channel 1 transmit data or infrared transmit data. rx1 41 i uart channel 1 receive data or infrared receive data. normal rxd input idles at logic 1 condition. the infrared pulses can be inverted internally prior to the decoder by fctr[4]. rts1# 46 o uart channel 1 request to send or general purpose output (active low). see description of rts0# pin. cts1# 42 i uart channel 1 clear to send or general purpose input (active low). see description of cts0# pin. dtr1# 47 o uart channel 1 data terminal ready or general purpose output (active low). see description of dts0# pin. dsr1# 43 i uart channel 1 data set ready or general purpose input (active low). see description of dsr0# pin. cd1# 44 i uart channel 1 carrier detect or general purpose input (active low). ri1# 45 i uart channel 1 ring indicator or general purpose input (active low). tx2 40 o uart channel 2 transmit data or infrared transmit data. rx2 33 i uart channel 2 receive data or infrared receive data. normal rxd input idles at logic 1 condition. the infrared pulses can be inverted internally prior to the decoder by fctr[4]. rts2# 38 o uart channel 2 request to send or general purpose output (active low). see description of rts0# pin. cts2# 34 i uart channel 2 clear to send or general purpose input (active low). see description of cts0# pin. dtr2# 39 o uart channel 2 data terminal ready or general purpose output (active low). see description of dts0# pin. dsr2# 35 i uart channel 2 data set ready or general purpose input (active low). see description of dsr0# pin. cd2# 36 i uart channel 2 carrier detect or general purpose input (active low). ri2# 37 i uart channel 2 ring indicator or general purpose intput (active low). tx3 28 o uart channel 3 transmit data or infrared transmit data. rx3 21 i uart channel 3 receive data or infrared receive data. normal rxd input idles at logic 1 condition. the infrared pulses can be inverted internally prior to the decoder by fctr[4]. rts3# 26 o uart channel 3 request to send or general purpose output (active low). see description of rts0# pin. cts3# 22 i uart channel 3 clear to send or general purpose input (active low).d. see description of cts0# pin. pin description n ame p in #t ype d escription
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 5 n ote : pin type: i=input, o=output, io= input/output, od=output open drain. dtr3# 27 o uart channel 3 data terminal ready or general purpose output (active low). see description of dts0# pin. dsr3# 23 i uart channel 3 data set ready or general purpose input (active low). see description of dsr0# pin. cd3# 24 i uart channel 3 carrier detect or general purpose input (active low). ri3# 25 i uart channel 3 ring indicator or general purpose input (active low). ancillary signals xtal1 50 i crystal or external clock input. xtal2 49 o crystal or buffered clock output. tmrck 31 i 16-bit timer/counter external clock input. enir 32 i infrared mode enable (active high). this pin is sampled during power up, fol- lowing a hardware reset (rst#) or soft-reset (register reset). it can be used to start up all 8 uarts in the infrared mode. the sampled logic state is transferred to mcr bit-6 in the uart. rst# 20 i reset (active low). the configuration and uart registers are reset to default values, see table-15. 16/68# 19 i intel or motorola data bus interface select. logic one selects intel bus inter- face and logic zero selects motorola interface. this input affects the function- ality of ior#, iow# and cs# pins. vcc 9,30,52 +5v or +3.3v supply, all inputs are 5v tolerant. gnd 10,29,51 power supply common, ground. pin description n ame p in #t ype d escription
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 6 description the XR16L784 (784) integrates the functions of 4 en- hanced 16550 uarts, a general purpose 16-bit tim- er/counter and an on-chip oscillator. the device con- figuration registers include a set of four consecutive interrupt source registers that provides interrupt-sta- tus for all 4 uarts, timer/counter and a sleep wake up indicator. each uart channel has its own 16550 uart compatible configuration register set for indi- vidual channel control, status, and data transfer. ad- ditionally, each uart channel has 64-byte of transmit and receive fifos, automatic rts/cts or dtr/dsr hardware flow control with hysteresis control, auto- matic xon/xoff and special character software flow control, programmable transmit and receive fifo trigger levels, fifo level counters, infrared encoder and decoder (irda ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and da- ta rate up to 6.25 mbps with 8x sampling clock rate or 3.125mbps in the 16x rate. the XR16L784 is a 5v and 3.3v device with 5 volt tolerant inputs. 1.0 XR16L784 registers the XR16L784 quad uart register set consists of the device configuration registers that are accessi- ble directly from the data bus for programming gener- al operating conditions of the uarts and monitoring the status of various functions. these functions in- clude all 4 channel uarts interrupt control and sta- tus, 16-bit general purpose timer control and status, sleep mode, soft-reset, and device identification and revision. also, each uart channel has its own set of internal uart configuration registers for its own op- eration control, status reporting and data transfer. these registers are mapped into a 256-byte of the data memory address space. the following para- graphs describe all the registers in detail. 1.1 device configuration register set the device configuration registers are directly acces- sible from the bus. this provides easy programming of general operating parameters to the 784 uart and for monitoring the status of various functions. the device configuration registers are mapped onto address 0x80-8f as shown on the register map in table 2 and figure 3. these registers provide global controls and status of all 4 channel uarts that in- clude interrupt status, 16-bit general purpose timer control and status, 8x or 16x sampling clock, sleep mode control, soft-reset control, simultaneous uart ini- tialization , and device identification and revision. f igure 3. t he XR16L784 r egisters m apping int0, int1, int2, int3, timer, sleep, reset 8-bit data bus interface channel 0 channel 1 channel 2 channel 3 device configuration registers 4 channel interrupts, 16-bit timer/counter, sleep, reset, dvid, drev uart[3:0] configuration registers 16550 compatible and exar enhanced registers 784regs 0x10-1f 0x00-0f 0x20-2f 0x30-3f 0x40-7f (reserved) 0x80-8f
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 7 . t able 1: XR16L784 r egister s ets a ddress [a7:a0] uart c hannel s pace r eference c omment 0x00 - 0x0f uart channel 0 registers (table 7 & 8) first 8 registers are 16550 compatible 0x10 - 0x1f uart channel 1 registers (table 7 & 8) 0x20 - 0x2f uart channel 2 registers (table 7 & 8) 0x30 - 0x3f uart channel 3 registers (table 7 & 8) 0x40 - 0x7f none reserved for xr16l788 octal uart 0x80 - 0x8f device configuration registers (table 2) interrupt registers and global controls t able 2: d evice c onfiguration r egisters a ddress [a7:a0] r ead / w rite r egister b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 0x80 r int0 source rsvd rsvd rsvd rsvd uart 3 uart 2 uart 1 uart 0 0x81 r int1 uart 2 bit 1 source bit 0 uart 1 bit 2 interrupt bit 1 source bit 0 uart 0 bit 2 interrupt bit 1 source bit 0 0x82 r int2 rsvd rsvd rsvd rsvd uart 3 bit 2 interrupt bit 1 source bit 0 uart 2 bit 2 0x83rint3 rsvdrsvdrsvdrsvdrsvdrsvdrsvdrsvd 0x84 r/w timer ctrl 0 0 0 0 clock source function select start timer enable timer int 0x85rtimer00000000 0x86 r/w timer lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x87 r/w timer msb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x88 r/w 8x mode rsvd rsvd rsvd rsvd uart 3 uart 2 uart 1 uart 0 0x89rreg 100000000 0x8a w reset rsvd rsvd rsvd rsvd reset uart 3 reset uart 2 reset uart 1 reset uart 0 0x8b r/w sleep rsvd rsvd rsvd rsvd enable sleep uart 3 enable sleep uart 2 enable sleep uart 1 enable sleep uart 0 0x8c r drev bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x8d r dvid bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x8er/wreg 20000000write to all uarts
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 8 1.1.1 the global interrupt source registers the XR16L784 has a global interrupt source register set that consists of 4 consecutive registers [int0, int1, int2 and int3]. register int3 is not used in the 784 uart, only in the 8-channel xr16l788. the 3 registers are in the device configuration register ad- dress space. all 4 registers default to logic zero (as indicated in square braces) for no interrupt pending. all 4 channel interrupts are enabled or disabled in each channels ier register. int0 shows individual status for each channel while int1 and int2 show the details of the source of each channels interrupt with its unique 3- bit encoding. figure 4 shows the 4 interrupt registers in sequence for clarity. the 16-bit timer and sleep wake-up interrupts are masked in the device configu- ration registers, timercntl and sleep. an interrupt is generated (if enabed) by the 784 when awakened from sleep if all 4 channels were placed in the sleep mode previously. each bit in the int0 register gives an indication of the channel that has requested service. int0 c hannel i nterrupt i ndicator : for example, bit-0 represents channel 0 and bit-3 in- dicates channel 3. bits 4 to 7 are reserved and re- mains at logic zero. logic one indicates the channel n [3:0] has called for service. the interrupt bit clears after reading the appropiate register of the interrupt- ing uart channel register (isr, lsr and msr). see table 9 for interrupt clearing details. int1 and int2 i nterrupt s ource l ocator int2 and int1 provide a 12-bit (3 bits per channel) encoded interrupt indicator. table 3 shows the 3 bit encoding and their priority order. the 16-bit timer time-out interrupt will show up only as a channel 0 in- terrupt . for other channels, interrupt 7 is reserved. . int3 (rsvd) [0x00] int2 [0x00] int1 [0x00] int0 [0x00] int0 register individual uart channel interrupt status rsvd rsvd rsvd rsvd ch-3 ch-2 ch-1 ch-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 f igure 4. t he g lobal i nterrupt r egisters , int0, int1, int2 and int3 reserved reserved reserved reserved channel-3 channel-2 channel-1 channel-0 int2 register int1 register int3 register interrupt registers, int0, int1, int2 and int3 bit 1 bit 2 bit 0 bit 1 bit 2 bit 0 bit 1 bit 2 bit 0 bit 1 bit 2 bit 0 bit 1 bit 2 bit 0 bit 1 bit 2 bit 0 bit 1 bit 2 bit 0 bit 1 bit 2 bit 0 int0 register bit-0 bit-1 bit-2 bit-3 bit-7 bit-4 bit-5 bit-6 rsvd rsvd rsvd ch-3 rsvd ch-2 ch-1 ch-0
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 9 1.1.2 general purpose 16-bit timer/counter. [timermsb, timelsb, timer, timecntl] ( default 0 x xx-xx-00-00) a 16-bit down-count timer for general purpose timer or counter. its clock source may be selected from in- ternal crystal oscillator or externally on pin tmrck. the timer can be set to be a single-shot for a one- time event or re-triggerable for a periodic event. an interrupt may be generated in the int register when the timer times out. it is controlled through 4 configu- ration registers [timercntl, timer, timelsb, timermsb]. these registers provide start/stop and re-triggerable or one-shot operation. the time-out output of the timer can be set to generate an inter- rupt for system or event alarm. t able 3: uart c hannel [3:0] i nterrupt s ource e ncoding and c learing p riority b it 2 b it 1 b it 0 i nterrupt s ource ( s ) and c learing x000 none 1001 rxrdy & rx line status (logic or of lsr[4:1]). rxrdy int clears by reading data in the rx fifo until it falls below the trigger level; rx line status int cleared after reading lsr register. 2010 rxrdy time-out: cleared when the fifo becomes empty. 3011 txrdy, thr or tsr (auto rs485 mode) empty, clears after reading isr register. 4100 msr, rts/cts or dtr/dsr delta or xoff/xon or special character detected. the first two clear after reading msr register; xoff/xon or special char. detect int clears after reading isr register. 5101 reserved. 6110 reserved. 7111 timer time-out, shows up as a channel 0 int. it clears after reading the timercntl register. reserved in other channels. f igure 5. t imer /c ounter circuit . tmrck osc. clock timercntl [3] 16-bit timer/counter timercntl [2] re-trigger single-shot timercntl [1] start/stop timercntl [0] tim er interrupt, c h-0 int=7 time-out timer interrupt enable single/re-triggerable timermsb and timerlsb (16-bit value) 0 1 0 1 0 1 no interrupt clock select
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 10 t able 4: timer control r egister timercntl [0] logic zero (default) disables timer-counter interrupt and logic one enables the interrupt, reading the timercntl clears the interrupt. timercnlt [1] logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter. timercntl [2] logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function. timercntl [3] logic zero (default) selects internal and logic one selects external clock to the timer/counter. timercntl [7:4] reserved (defaults to zero).
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 11 timer [7:0] (default 0x00): reserved. timermsb [7:0] and timerlsb [7:0] timermsb and timerlsb form a 16-bit value. the least-significant bit of the timer is being bit [0] of the timerlsb with most-significant-bit being bit [7] in timermsb. reading the timercntl register will clear its interrupt. default value is zero upon pow- erup and reset. 1.1.3 8xmode [7:0] (default 0x00) each bit selects 8x or 16x sampling rate for that uart channel, bit-0 is channel 0. logic 0 (default) selects normal 16x sampling with logic one selects 8x sampling rate. transmit and receive data rates will double by selecting 8x. 1.1.4 rega [7:0] is reserved (default 0x00) 1.1.5 reset [7:0] (default 0x00) the 8-bit reset register [reset] provides the soft- ware with the ability to reset individual uart(s) when there is a need. each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. all registers in that channel will be reset to the default condition, see ta b l e 1 5 for details. as an example, bit- 0 =1 resets uart channel 0 with bit-3=1 resets channel 3. 1.1.6 sleep [7:0] (default 0x00) the 8-bit sleep register enables each uart sepa- rately to enter sleep mode. sleep mode reduces power consumption when the system needs to put the uart(s) to idle. the uart enters sleep mode when there is no interrupt pending. when all 4 uarts are put to sleep, the on-chip oscillator shuts off to fur- ther conserve power. in this case, the quad uart is awakened by any of the uart channel on from a re- ceive data byte or a change on the modem port (cts#, dsr#, cd# and ri#). the uart is ready af- ter 32 crystal clocks to ensure full functionality. also, a special interrupt is generated with an indication of no pending interrupt. logic 0 (default) and logic 1 dis- able and enable sleep mode respectively. 1.1.7 device identification and revision there are 2 internal registers that provide device identification and revision, dvid and drev registers. the 8-bit content in the dvid register provides device identification. a return value of 0x24 from this register timercntl register rsvd rsvd rsvd rsvd clock select single/ re-trigger start/ stop int enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 timermsb register bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 timerlsb register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 16-bit timer/counter programmable registers rega [7:0] is reserved (default 0x00) rsvd rsvd rsvd rsvd ch-3 ch-2 ch-1 ch-0 8xmode register individual uart channel 8x clock mode enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 rsvd rsvd rsvd rsvd ch-3 ch-2 ch-1 ch-0 reset re g ister individual uart channel reset enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 sleep register individual uart channel sleep enable rsvd rsvd rsvd rsvd ch-3 ch-2 ch-1 ch-0
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 12 indicates the device is a XR16L784. the drev regis- ter returns a 8-bit value of 0x01 for revision a, 0x02 for revision b and so on. this information is very use- ful to the software driver for identifying which device it is communicating with and to keep up with revision changes. dvid [7:0] default 0x24) device identification for the type of uart. the upper nibble indicates it is a xr16l78x series with lower nibble indicating the number of channels. examples: XR16L784 = 0x24 xr16l788 = 0x28 drev [7:0] (default (0x01) revision number of the XR16L784. a 0x01 repre- sents "revision-a" with 0x02 for rev-b and so forth. 1.1.8 regb [7:0] (default 0x00) regb register provides a control for simultaneous write to all 4 uarts configuration registers or individ- ually. this is very useful for device intialization in the power up and reset routines. 2.0 crystal oscillator / buffer the 784 includes an on-chip oscillator (xtal1 and xtal2). the crystal oscillator provides the system clock to the baud rate generators (brg) in each of the 4 uarts, the 16-bit general purpose timer/ counter and internal logics. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. for programming details, see pro- grammable baud rate generator on page 13 . the on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant with 10-22 pf capacitance load, 100ppm) connected externally between the xtal1 and xtal2 pins (see figure 6 ). alternatively, an external clock can be con- nected to the xtal1 pin to clock the 4 internal baud rate generators for standard or custom rates. typical oscillator connections are shown in figure 6. for fur- ther reading on oscillator circuit please see applica- tion note dan108 on exars web site. 3.0 transmit and receive data each uart channel has a transmit holding register (thr) and a receive holding register (rhr). the thr and rhr registers are 16550 compatible so their access is limited to 8-bit format. the software driver must separately read the lsr content for the associated error flags before reading the data byte. 3.1 fifo data loading and unloading through the uart channel regis- ters, thr and rhr. the thr and rhr register addresses for channel 0 to channel 3 is shown in ta b l e 5 below. the thr and rhr for channels 0 to 3 are located at address 0x00, 0x10, 0x20 and 0x30 respectively. transmit data byte is loaded to the thr when writting to that address and receive data is unloaded from the rhr register when reading from that address. both thr and rhr registers are 16c550 compatible in 8-bit format, so each bus operation can only write or read in bytes. regb[0] logic 0 (default) write to each uart configuration registers individually. logic 1 enables simultaneous write to all 4 uarts configuration register. use- ful during device initialization. regb[7:1] reserved f igure 6. t ypical oscillator connections c1 22-47pf c2 22-47pf 14.7456 mhz xtal1 xtal2 r=300k to 400k
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 13 . 4.0 uart there are 4 uarts [channel 3:0] in the 784. each has its own 64-byte of transmit and receive fifo, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting. eight additional registers per uart were added for the exar enhanced features. 4.1 p rogrammable b aud r ate g enerator each uart has its own baud rate generator (brg) with a prescaler for the transmiter and receiver. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the output of the prescaler clocks to the brg. the brg further divides this clock by a programmable di- visor between 1 and (2 16 -1) to obtain a 16x or 8x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll and dlm registers) defaults to a random value upon power up. therefore, the brg must be programmed during initialization to the operating data rate. programming the baud rate generator registers dlm and dll provides the capability of selecting the operating data rate. ta b l e 6 shows the standard data rates available with a 14.7456 mhz crystal or external clock at 16x clock rate. at 8x sampling rate, these data rates would double. when using a non-standard t able 5: t ransmit and r eceive d ata r egister , 16c550 compatible thr and rhr address locations for ch0 to ch3 (16c550 compatible) ch0 0x00 write thr ch0 0x00 read rhr ch1 0x10 write thr ch1 0x10 read rhr ch2 0x20 write thr ch2 0x20 read rhr ch3 0x30 write thr ch3 0x30 read rhr 784thr rhr1 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 f igure 7. b aud r ate g enerator xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x or 8x sampling rate clock to transmitter and receiver to other channels baud rate generator logic
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 14 data rate crystal or external clock, the divisor value can be calculated for channel n with the following equation(s). 4.2 a utomatic rts/dtr h ardware f low c on - trol o peration automatic rts/dtr flow control is used to prevent data overrun to the local receiver fifo. the rts#/ dtr# output pin is used to request remote unit to suspend/resume data transmission. the flow control features are individually selected to fit specific appli- cation requirement (see figure 8): ? select rts (and cts) or dtr (and dsr) through mcr bit-2. ? enable auto rts/dtr flow control using efr bit-6. ? the auto rts/dtr function must be started by asserting rts/dtr# output pin (mcr bit-0 or 1 to logic 1 after it is enabled. ? enable rts/dtr interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts#/dtr# pin makes a transition: isr bit-5 will be set to 1. ? select hysteresis values when used with program- mable rx fifo trigger levels. 4.2.1 automatic cts/dsr hardware flow con- trol operation ? automatic cts/dsr flow control is used to prevent data overrun to the remote receiver fifo. the cts/dsr pin is monitored to suspend/restart local transmitter. the flow control features are individu- ally selected to fit specific application requirement (see figure 8): ? select cts (and rts) or dsr (and dtr) through cr bit-2. ? enable auto cts/dsr flow control using efr bit- 7. ? enable cts/dsr interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts#/dsr# pin makes a transition: isr bit-5 will be set to 1, and uart will suspend tx transmissions as soon as the stop bit of the charac- ter in process is shifted out. transmission is resumed after the cts#/dsr# input returns to logic 0, indicating more data may be sent. divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16), when 8xmode- bit n is 0 divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 8), when 8xmode- bit n is 1 t able 6: t ypical data rates with a 14.7456 mh z crystal or external clock at 16x s ampling o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 15 4.3 i nfrared m ode each uart in the 784 includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.1. the input pin enir conve- niently activates all 4 uart channels to start up in the infrared mode. this global control pin enables the mcr bit-6 function in every uart channel register. after power up or a reset, the software can overwrite mcr bit-6 if so desired. enir and mcr bit-6 also disable the receiver while the transmitter is sending data. this prevents echoed data from reaching the receiver. the global activation enir pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. when the infrared feature is enabled, the transmit da- ta outputs, tx[3:0], would idle at logic zero level. likewise, the rx [3:0] inputs assume an idle level of logic zero. the infrared encoder sends out a 3/16 of a bit wide high-pulse for each 0 bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consump- tion. see figure 9 below. the infrared decoder receives the input pulse from the infrared sensing diode on rx pin. each time it senses a light pulse, it returns a logic zero to the data bit stream. the decoder also accepts (when fctr f igure 8. a uto rts/dtr and cts/dsr f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to send data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger level, uarta activates its rxa data ready interrupt (5) and con- tinues to receive and put data into its fifo. if interrupt service latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper threshold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. uartb stops or finishes sending the data bits in its transmit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next re- ceive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 16 bit-4 = 1) an inverted ir-encoded input signal. this option supports active low instead of normal active high pulse from some infrared modules in the mar- ket. 4.4 i nternal l oopback each uart channel provides an internal loopback capability for system diagnostic purposes. the inter- nal loopback mode is enabled by setting mcr regis- ter bit-4 to logic 1. all regular uart functions operate normally. figure 10 shows how the modem port sig- nals are re-configured. transmit data from the trans- mit shift register output is internally routed to the re- ceive shift register input allowing the system to re- ceive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. f igure 9. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 17 4.5 uart channel configuration regis- ters and address decoding. the 4 sets of uart configuration registers are de- coded using address lines a4 to a7 as show below. address lines a0 to a3 select the 16 registers in each channel. the first 8 registers are 16550 compatible with exar enhanced feature registers located on the next 8 addresses. f igure 10. i nternal l oop b ack tx [7:0] r x [7:0] modem / general purpose control logic internal bus lines and control signals r ts# [7:0] mcr bit-4=1 vcc vcc vcc transmit shift register r eceive shift register c ts# [7:0] d tr # [7:0] d sr # [7:0] r i# [7:0] c d # [7:0] op1# op2# rts# cts# dtr# dsr# ri# cd# a7 a6 a5 a4 uart c hannel s election 0000 0 0001 1 0010 2 0011 3
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 18 . t able 7: uart channel configuration registers. a ddress r egister r ead /w rite c omments a3 a2 a1 a0 16550 c ompatible 0 0 0 0 rhr - receive holding reg thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 0 dll - baud rate generator divisor, least-significant-byte (lsb) read/write lcr[7] = 1 0 0 0 1 dlm - baud rate generator divisor, most-significant-byte (msb) read/write lcr[7] = 1 0 0 0 1 ier - interrupt enable reg read/write lcr[7] = 0 0 0 1 0 isr - interrupt status reg fcr - fifo control reg read-only write-only 0 0 1 1 lcr - line control reg read/write 0 1 0 0 mcr - modem control reg read/write 0 1 0 1 lsr - line status reg reserved read-only write-only 0 1 1 0 msr - modem status reg reserved read-only write-only 0 1 1 1 spr - scratch pad reg read/write e nhanced r egister 1 0 0 0 fctr read/write 1 0 0 1 efr - enhanced function reg read/write 1 0 1 0 txcnt - transmit fifo level counter txtrg - transmit fifo trigger level read-only write-only 1 0 1 1 rxcnt - receive fifo level counter rxtrg - receive fifo trigger level read-only write-only 1 1 0 0 xoff-1 - xoff character 1 xchar write-only read-only xon,xoff rcvd. flags 1 1 0 1 xoff-2 - xoff character 2 reserved write-only read-only 1 1 1 0 xon-1 - xon character 1 reserved write-only read-only 1 1 1 1 xon-2 - xon character 2 reserved write-only read-only
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 19 n ote 2: mcr bits 2 and 3 (op1 and op2 outputs) are not available in the XR16L784. they are present for 16c550 compatibility during internal loopback, see figure 10. t able 8: uart channel configuration registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 0 0 0 0 rhr r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 0 thr w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=0 0 0 0 0 dll r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 0 1 dlm r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 0 0 0 1 ier r/w 0/ cts/dsr# int. enable 0/ rts/dtr# int. enable 0/ xon/xoff/ sp. char. int. enable 0 modem status int. enable rx line status int. enable tx empty int. enable rx data int. enable 0 0 1 0 isr r 0/ fifos enable 0/ fifos enable 0/ deltaflow cntl 0/ xoff/spe- cial char int source bit-3 int source bit-2 int source bit-1 int source bit-0 0 0 1 0 fcr w 0/ rx fifo trigger 0/ rx fifo trigger 0/ tx fifo trigger 0/ tx fifo trigger dma mode tx fifo reset rx fifo reset fifos enable 0 0 1 1 lcr r/w divisor enable set tx break set parity even par- ity parity enable stop bits word length bit-1 word length bit-0 0 1 0 0 mcr r/w 0/ brg pres- caler 0/ ir enable 0/ xonany internal lopback enable op2 2 op1 2 / rts/dtr flow sel rts# pin control dtr# pin control 0 1 0 1 lsr r/w rx fifo e rror tsr empty thr empty rx break rx fram- ing error rx parity error rx over- run rx data ready 0 1 1 0 msr r cd ri dsr cts delta cd# delta ri# delta dsr# delta cts# msr w 0/ rs485 dly-3 0/ rs485 dly-2 0/ rs485 dly-1 0/ rs485 dly-0 reserved reserved reserved reserved 0 1 1 1 spr r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 user data 1 0 0 0 fctr r/w trg table bit-1 trg table bit-0 auto rs485 enable invert ir rx input rts/dtr hyst bit-3 rts/dtr hyst bit-2 rts/dtr hyst bit-1 rts/dtr hyst bit-0 1 0 0 1 efr r/w auto cts/ dsr enable auto rts/ dtr enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5] msr[7:4] software flow cntl bit-3 software flow cntl bit-2 software flow cntl bit-1 software flow cntl bit-0 1 0 1 0 tfcnt r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 0 tftrg w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 1 rfcnt r bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 1 rftrg w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 0 xchar r xon det. indicator xoff det. indicator self-clear after read 1 1 0 0 xoff1 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 1 xoff2 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 0 xon1 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 1 xon2 w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 20 4.6 t ransmitter the transmitter section comprises of 64 bytes of fifo, a byte-wide transmit holding register (thr) and an 8-bit transmit shift register (tsr). thr re- ceives a data byte from the host (non-fifo mode) or a data byte from the fifo when the fifo is enabled by fcr bit-0. tsr shifts out every data bit with the 16x or 8x internal clock. a bit time is 16 or 8 clock pe- riods. the transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if enabled, and adds the stop bit(s). the status of the thr and tsr are reported in the line status regis- ter (lsr bit-5 and bit-6). 4.6.1 transmit holding register (thr) the transmit holding register is an 8-bit register pro- viding a data interface to the host processor. the host writes transmit data byte to the thr to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-significant-bit (bit- 0) becomes first data bit to go out. the thr is also the input register to the transmit fifo of 64 bytes when fifo operation is enabled by fcr bit-0. every time a write operation is made to the transmit holding register, its fifo data pointer is automatically bumped to the next sequential data location. a thr empty interrupt can be generated when ier bit-1 is set to logical 1. 4.6.2 transmitter operation in non-fifo the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. 4.6.3 transmitter operation in fifo the host may fill the transmit fifo with up to 64 bytes of transmit data. the thr empty flag (lsr bit- 5) is set whenever the fifo is empty. the thr emp- ty flag can generate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed trigger level (see txtrg register). the transmit empty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr becomes completely empty. furthermore, with the rs485 half- duplex direction control enabled (fctr bit-5=1), the source of the transmit empty interrupt changes to tsr empty instead of thr empty. this is to ensure the rts# output is not changed until the last stop bit of the last character is shifted out. 4.6.4 auto rs485 operation the auto rs485 half-duplex direction control chang- es the behavior of the transmitter when enabled by fctr bit-5. it de-asserts rts# or dtr# after a spec- ified delay indicated in msr[7:4] following the last stop bit of the last character that has been transmit- ted. this helps in turning around the transceiver to re- ceive the remote stations response. the delay opti- mizes the time needed for the last transmission to reach the farthest station on a long cable network be- fore switching off the line driver. this delay prevents undesirable line signal disturbance that causes signal degradation. the auto rs485 half-duplex direction contol also changes the transmitter empty interrupt to tsr empty instead of thr empty. f igure 11. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transmit shift r eg ister (tsr ) data byte l s b m s b th r interrupt (isr bit-1) enabled by ier bit-1 txnofifo 16x or 8x c lock (8xmode r eg ister)
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 21 4.7 r eceiver the receiver section contains an 8-bit receive shift register (rsr) and a byte-wide receive holding register (rhr). the rsr uses the 16x or 8x clock for timing. it verifies and validates every bit on the in- coming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x (or 8x) clock rate. after 8 (or 4) clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validat- ed. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false fram- ing. if there were any error(s), they are reported in the lsr register bits 1- 4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt up- on receiving a character or delay until it reaches the fifo trigger level. furthemore, data delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach the re- ceive fifo trigger level. this time-out delay is 4 word lengths as defined by lcr[1,0] plus 12 bits time. the rhr interrupt is enabled by ier bit-0. 4.8 r egisters 4.8.1 receive holding register (rhr) the receive holding register is a 8-bit register that holds a receive data byte from the receive shift regis- ter (rsr). it provides the receive data interface to the host processor. the host reads the receive data byte on this register whenever a data byte is trasferred from the rsr. rhr is also part of the receive fifo of 64 bytes by 11-bit wide, 3 extra bits are for the error flags to be in lsr register. when the fifo is enabled by fcr bit-0, it acts as the first-out register of the fifo as new data are put over the first-in register. ev- ery time a read operation is made to the receive hold- ing register, its fifo data pointer is automatically bumped to the next sequential data location. also, the error flags associated with the data byte are immedi- ately updated onto the line status register (lsr) bits 1-4. 4.8.2 baud rate generator divisors (dll and dlm) the baud rate generator (brg) is a 16-bit counter that generates the data rate for the transmitter and receiver. the rate is programmed through registers dll and dlm which are only accessible when lcr bit-7 is set to logic 1. see programmable baud rate generator section for more detail. f igure 12. t ransmiitter o peration in fifo and f low c ontrol m ode transm it data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below programmed trigger level (txtrg) and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo (64-byte) txfifo1 16x or 8x clock (8xmode register) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 22 4.8.3 interrupt enable register (ier) the interrupt enable register (ier) masks the inter- rupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are reported in the interrupt status register (isr) register and also encoded in int (int0-int3) register in the device configuration registers. 4.9 ier versus r eceive fifo i nterrupt m ode o peration when the receive fifo (fcr bit-0 = a logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the rhr interrupts (see isr bits 3 and 4) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the pro- grammed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared when the fifo drops below the trigger level. f igure 13. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data h olding register (rhr) rxfifo1 16x or 8x clock (8xmode register) receive data characters data bit validation error flags in lsr bits 3:1 f igure 14. r eceiver o peration in fifo and f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x or 8x sampling clock (8xmode reg.) error flags (64-sets) error flags in lsr bits 3:1 64 bytes by 11- bit wide fifo receive data characters fifo trigger=48 example: - fifo trigger level set at 48 bytes - rts/dtr hyasteresis set at +/-8 chars. data fills to 56 data falls to 40 data bit validation receive data fifo (64-byte) receive data receive data byte and errors rhr interrupt (isr bit-2) is programmed at fifo trigger level (rxtrg). fifo is enable by fcr bit-0=1 rts#/dtr# de-asserts when data fills above the trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-2. rts#/dtr# re-asserts when data falls below the trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-2.
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 23 c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is reset when the fifo is empty. 4.10 ier versus r eceive /t ransmit fifo p olled m ode o peration when fcr bit-0 equals a logic 1 for fifo enable; resetting ier bits 0-3 enables the XR16L784 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit 1-4 provides the type of receive data er- rors encountered for the data byte in rhr, if any. c. lsr bit-5 indicates thr is empty. d. lsr bit-6 indicates when both the transmit fifo and tsr are empty. e. lsr bit-7 indicates the ored function of errors in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data character in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. logic 0 = disable the receive data ready interrupt. (default) logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this interrupt is associated with bit-5 in the lsr reg- ister. an interrupt is issued whenever the thr be- comes empty in the non-fifo mode or when data in the fifo falls below the programmed trigger level, in the fifo mode. logic 0 = disable transmit holding register empty interrupt. (default) logic 1 = enable transmit holding register empty interrupt. ier[2]: receive line status interrupt enable any of the lsr register bits 1,2,3 or 4 becomes ac- tive will generate an interrupt to inform the host con- troller about the error status of the current data byte in fifo. logic 0 = disable the receiver line status interrupt. (default) logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable logic 0 = disable the modem status register interrupt. (default) logic 1 = enable the modem status register interrupt. ier[4]: reserved . ier[5]: xoff interrupt enable (requires efr bit- 4=1) logic 0 = disable the software flow control, receive xoff interrupt. (default) logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details. ier[6]: rts# output interrupt enable (requires efr bit-4=1) logic 0 = disable the rts# interrupt. (default ). logic 1 = enable the rts# interrupt. the uart is- sues an interrupt when the rts# pin makes a transi- tion. ier[7]: cts# input interrupt enable (requires efr bit-4=1) logic 0 = disable the cts# interrupt. (default). logic 1 = enable the cts# interrupt. the uart is- sues an interrupt when cts# pin makes a transition. 4.11 i nterrupt s tatus r egister (isr) the uart provides multiple levels of prioritized inter- rupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current highest pending interrupt level to be serviced, others queue up for next service. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 9, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt lev- els. 4.11.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by the a 4-char plus 12 bits delay timer if data doesnt reach fifo trigger level. ? txrdy is by lsr bit-5 in the non-fifo mode, below fifo trigger level in the fifo mode, or bit-6 in auto rs485 control. ? msr is by any of the msr bits, 0, 1, 2 and 3. ? receive xon / xoff/special character is by detection of a xon, xoff or special character.
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 24 ? cts#/dsr# is by a change of state on the input pin with auto flow control enabled by efr bit-7, and depending on selection on mcr bit-2. ? rts#/dtr# is when its receiver changes the state of the output pin during auto rts/dtr flow control enabled by efr bit-6 and selection of mcr bit-2. 4.11.2 interrupt clearing: ? lsr interrupt is cleared by a read of the lsr regis- ter. ? rxrdy is cleared by reading data until fifo falls below the rx fifo trigger level. ? rxrdy time-out is cleared by emptying the fifo. ? txrdy interrupt is cleared by a read of the isr register. ? msr interrupt is cleared by a read of the msr reg- ister. ? xon, xoff or special character interrupt is cleared by a read of the isr. ? rts#/dtr# output status change interrupts is cleared by a read of the isr register. ? cts#/dsr# input status change interrupts is cleared by a read of the msr register. isr[0]: interrupt status logic 0 = an interrupt is pending and the isr con- tents may be used as a pointer to the appropriate in- terrupt service routine. logic 1 = no interrupt pending. (default condition) isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (see interrupt source ta b l e 9 ). isr[5:4]: interrupt status these bits are enabled when efr bit-4 is set to a log- ic 1. isr bit-4 indicates that the receiver detected a data match of the xon or xoff character(s). n ote : note that once set to a logic 1, the isr bit-4 will stay a logic 1 until a xon character is received. isr bit-5 indi- cates that cts#/dsr# or rts#/dtr# has changed state. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disabled. they are set to a logic 1 when the fifos are enabled. 4.11.3 fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr bit-0: tx and rx fifo enable logic 0 = disable the transmit and receive fifo. (de- fault). logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is active. logic 0 = no receive fifo reset. (default) logic 1 = reset the receive fifo pointers and fifo level counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is active. t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of the interrupt + l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0001 1 0 lsr (receiver line status register) 2 0001 0 0 rxrdy (received data ready) 3 0011 0 0 rxrdy (receive data time-out) 4 0000 1 0 txrdy ( transmitter holding register empty) 5 0000 0 0 msr (modem status register) 6 0100 0 0 rxrdy (received xon/xoff or special character) 7 1000 0 0 cts#/dsr#, rts#/dtr# change of state x 0000 0 1 none (default)
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 25 logic 0 = no transmit fifo reset. (default) logic 1 = reset the transmit fifo pointers and fifo level counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select this bit has no effect since txrdy and rxrdy pins are not available in this device. it is provided for lega- cy software. logic 0 = set dma to mode 0. (default) logic 1 = set dma to mode 1. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = one) the fctr bits 6-7 are associated with these 2 bits by selecting one of the four tables. the 4 user select- able trigger levels in 4 tables are supported for com- patibility reasons. these 2 bits set the trigger level for the transmit fifo interrupt. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 10 be- low shows the selections. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits 6-7 are associated with these 2 bits. these 2 bits are used to set the trigger level for the receiver fifo interrupt. ta b l e 1 0 shows the complete selections. 4.11.4 line control register (lcr) the line control register is used to specify the asyn- chronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1-0]: tx and rx word length select these two bits specify the word length to be transmit- ted or received. t able 10: t ransmit and r eceive fifo t rigger l evel s election fctr b it -7 fctr b it -6 fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel c ompatibility 00 0 0 1 1 0 1 0 1 00 1 (default) 4 8 14 1 (default) table-a. 16c550, 16c2550, 16c2552, 16c554, 16c580 compatible. 01 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 table-b. 16c650a compatible. 10 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 table-c. 16c654 compatible. 1 1xxxxprogrammableprogrammable table-d. 16c850, 16c2850, 16c2852, 16c854, 16c864, 16c872 compatible.
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 26 lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bit in con- junction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the parity bit is a simple way used in communications for data integrity check. see ta b l e 1 1 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the trans- mission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted character. the receiver must be programmed to check the same for- mat. (default). ? logic 1 = even parity is generated by forcing an even the number of logic 1s in the transmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit-5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced. (default) ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable ? when enabled the break control bit it causes a break condition to be transmitted (the tx output is forced to a space, logic 0, state). this condition remains until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition. (default) ? logic 1 = forces the transmitter output (tx) to a space, logic 0, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected. (default) ? logic 1 = divisor latch registers are selected. 4.11.5 modem control register (mcr) or gen- eral purpose outputs control. this register controls the serial interface signals with the modem or a peripheral device. modem control register (mcr) the mcr register is used for controlling the modem interface signals or general purpose inputs/outputs. mcr[0]: dtr# pins the dtr# pin may be used for automatic hardware flow control enabled by efr bit-6 and mcr bit-2=1. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force dtr# output to a logic 1. (default) ? logic 1 = force dtr# output to a logic 0. mcr[1]: rts# pins the rts# pin may be used for automatic hardware flow control by enabled by efr bit-6 and mcr bit- 2=0. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force rts# output to a logic 1. (default) bit-1 bit-0 w ord length 0 0 5 (default) 01 6 10 7 11 8 bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 16,7,8 2 t able 11: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection xx0 no parity 0 0 1 odd parity 011 even parity 1 0 1 force parity to mark, 1 1 1 1 forced parity to space, 0
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 27 ? logic 1 = force rts# output to a logic 0. mcr[2]: rts/cts or dtr/dsr for auto flow control dtr# or rts# auto hardware flow control select. this bit is in effect only when auto rts/dtr is en- abled by efr bit-6. ? logic 0 = rts# (rx side) and cts# (tx side) pins are used for auto hardware flow control. ? logic 1 = dtr# (rx side) and dsr# (tx side) pins are used for auto hardware flow control. mcr[3]: reserved. logic zero is default. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode. (default) ? logic 1 = enable local loopback mode, see loop- back section and figure 10 . mcr[5]: xon-any enable ? logic 0 = disable xon-any function (for 16c550 compatibility). (default). ? logic 1 = enable xon-any function. in this mode any rx character received will enable xon, resume data transmission. mcr[6]: infrared encoder/decoder enable ? logic 0 = enable the standard modem receive and transmit input/output interface. ? logic 1 = enable infrared irda receive and transmit inputs/outputs. while in this mode, the tx/rx out- put/input are routed to the infrared encoder/ decoder. the data input and output levels will con- form to the irda infrared interface requirement. as such, while in this mode the infrared tx output will be a logic 0 during idle data conditions. fctr bit-4 may be selected to invert the rx input signal level going to the decoder for infrared modules that pro- vide rather an inverted output. ? logic 0 is the default unless the ir mode is enabled during start-up via hardware pin enir. mcr[7]: clock prescaler select ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the pro- grammable baud rate generator without further modification, i.e., divide by one. (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate gen- erator, hence, data rates become one forth. 4.11.6 line status register (lsr) this register provides the status of data transfers be- tween the uart and the host. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo. (default). ? logic 1 = data has been received and is saved in the receive holding register or fifo. lsr[1]: receiver overrun flag ? logic 0 = no overrun error. (default) ? logic 1 = overrun error. a data overrun error condi- tion occurred in the receive shift register. this hap- pens when additional data arrives while the fifo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error flag ? logic 0 = no parity error. (default) ? logic 1 = parity error. the receive character in rhr does not have correct parity information and is suspect. this error is associated with the char- acter available for reading in rhr. lsr[3]: receive data framing error flag ? logic 0 = no framing error. (default) ? logic 1 = framing error. the receive character did not have a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break flag ? logic 0 = no break condition. (default) ? logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, mark or logic 1. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indi- cator. this bit indicates that the transmitter is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the host when the thr interrupt enable is set. the thr bit is set to a logic 1 when the last data byte is trans- ferred from the transmit holding register to the trans- mit shift register. the bit is reset to logic 0 concurrent- ly with the data loading to the transmit holding regis- ter by the host. in the fifo mode this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. lsr[6]: transmit shift register empty flag this bit is the transmit shift register empty indicator. this bit is set to a logic 1 whenever the transmitter
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 28 goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error. (default) ? logic 1 = an indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in the fifo. 4.11.7 modem status register (msr) - read only this register provides the current state of the modem interface signals, or other peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outpus when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringing signal. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3. msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by au- to cts (efr bit-7) and rts/cts flow control select (mcr bit-2). auto cts flow control allows starting and stopping of local data transmissions based on the modem cts# signal. a logic 1 on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. normally msr bit-4 bit is the compliment of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# (active high, logical 1). this input may be used for auto dtr/dsr flow control function, see auto \hardware flow control section. normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr regis- ter. the dsr# input may be used as a general pur- pose input when the modem interface is not used. msr[6]: ri input status ri# (active high, logical 1). normally this bit is the compliment of the ri# input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status cd# (active high, logical 1). normally this bit is the compliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.11.8 modem status register (msr) - write only the upper four bits 4-7 of this register sets the delay in number of bits time for the auto rs485 turn around from transmit to receive. msr [7:4] when auto rs485 feature is enabled (fctr bit-5=1) and rts# output is connected to the enable input of a rs-485 transceiver. these 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last transmitted character. this delay controls when to change the state of rts# output. this delay is very useful in long-cable networks. table 12 shows the selection. the bits are enabled by efr bit-4.
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 29 4.11.9 scratch pad register (spr) this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (de- fault) after a reset or a power off-on cycle. 4.11.10 feature control register (fctr) this register controls the uart enhanced functions that are not available on st16c554 or st16c654. fctr [3:0] - auto rts/dtr flow control hystere- sis select these bits select the auto rts/dtr flow control hys- teresis and only valid when tx and rx trigger table- d is selected (fctr bit-6 and 7 are set to logic 1). the rts/dtr hysteresis is referenced to the rx fifo trigger level. after reset, these bits are set to logic 0 selecting the next fifo trigger level for hard- ware flow control. ta b l e 1 3 below shows the 16 select- able hysteresis levels. t able 12: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive msr[7] msr[6] msr[5] msr[4] d elay in d ata b it ( s ) t ime 0000 0 0001 1 0010 2 0011 3 0100 4 9101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 t able 13: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected fctr b it - 3 fctr b it - 2 fctr b it - 1 fctr b it - 0 rts/dtr h ysteresis ( characters ) 0000 0 0001 +/- 4 0010 +/- 6 0011 +/- 8 0100 +/- 8 0101 +/- 16
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 30 fctr[4]: infrared rx input logic select 0 = select rx input as active high encoded irda da- ta, normal, (default). 1 = select rx input as active low encoded irda data, inverted. fctr[5]: auto rs485 enable auto rs485 half duplex control enable/disable. ? 0 = standard st16c550 mode. transmitter gener- ates an interrupt when transmit holding register (thr) becomes empty. transmit shift register (tsr) may still be shifting data bit out. ? 1 = enable auto rs485 half duplex direction con- trol. rts# output changes its logic level from 1 to 0 when finished sending the last stop bit of the last character out of the tsr register. it changes back to logic level 1 from 0 when a data byte is loaded into the thr or transmit fifo. the change to logic 1 occurs prior sending the start-bit. it also changes the transmitter interrupt from transmit holding to transmit shift register (tsr) empty. fctr[7:6]: tx and rx fifo trigger table select these 2 bits select the transmit and receive fifo trig- ger level table a, b, c or d. when table a, b, or c is selected the auto rts flow control trigger level is set to "next fifo trigger level" for compatibility to st16c550 and st16c650 series. rts/dtr# trig- gers on the next level of the rx fifo trigger level, in other words, one fifo level above and one fifo lev- el below. see ta b l e 1 0 for complete selection with fcr bit 4-5 and fctr bit 6-7. for example, if table c is used on the receiver with rx fifo trigger level set to 56 bytes, rts/dtr# output will de-assert at 60 and re-assert at 16. 4.11.11 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide single or dual consecutive character software flow control selection (see table 14). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. cau- tion: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (dis- able) before programming a new setting. 0110 +/- 24 0111 +/- 32 1100 +/- 12 1101 +/- 20 1110 +/- 28 1111 +/- 36 1000 +/- 40 1001 +/- 44 1010 +/- 48 1011 +/- 52 t able 13: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected fctr b it - 3 fctr b it - 2 fctr b it - 1 fctr b it - 0 rts/dtr h ysteresis ( characters )
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 31 efr bit 0-3: software flow control select combinations of software flow control can be select- ed by programming these bits. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables the functions in ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled, logic 1. ? logic 0 = modification disable/latch enhanced fea- tures. ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are set to a logic 0 to be compatible with st16c554 mode. (default). ? logic 1 = enables the enhanced functions. when this bit is set to a logic 1 all enhanced features are enabled. efr[5]: special character detect enable ? logic 0 = special character detect disabled. (default) ? logic 1 = special character detect enabled. the uart compares each incoming receive character with data in xoff-2 register. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 corresponds with the lsb bit for the receive character. if flow control is set for compar- ing xon1, xoff1 (efr [1:0]=10) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]=01) then flow control works normally, but xoff2 will not go to the fifo, and will generate an xoff interupt and a special character interrupt. efr[6]: auto rts or dtr flow control enable rts#/dtr# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts/dtr is selected, an interrupt will be generated when the receive fifo is filled to the programmed trigger level and rts/dtr# will de-assert to a logic 1 at the next upper trigger or selected hysteresis level. rts/dtr# will return to a logic 0 when fifo data falls below the next lower trigger or selected hystere- sis level (see fctr bits 4-7). the rts# or dtr# out- put must be asserted (logic 0) before the auto rts/ t able 14: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0000 no tx and rx flow control (default and reset) 00xx no transmit flow control 10xx transmit xon1/xoff1 01xx transmit xon2/xoff2 11xx transmit xon1 and xon2/xoff1 and xoff2 xx00 no receive flow control xx10 receiver compares xon1/xoff1 xx01 receiver compares xon2/xoff2 1011 transmit xon1/ xoff1, receiver compares xon1 or xon2, xoff1 or xoff2 0111 transmit xon2/xoff2, receiver compares xon1 or xon2, xoff1 or xoff2 1111 transmit xon1 and xon2/xoff1 and xoff2, receiver compares xon1 and xon2/xoff1 and xoff2 0011 no transmit flow control, receiver compares xon1 and xon2/xoff1 and xoff2
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 32 dtr can take effect. the selection for rts# or dtr# is through mcr bit-2. rts/dtr# pin will function as a general purpose output when hardware flow control is disabled. ? logic 0 = automatic rts/dtr flow control is dis- abled. (default) ? logic 1 = enable automatic rts/dtr flow control. efr[7]: auto cts flow control enable automatic cts or dsr flow control. ? logic 0 = automatic cts/dsr flow control is dis- abled. (default) ? logic 1 = enable automatic cts/dsr flow control. transmission stops when cts/dsr# pin de- asserts to logic 1. transmission resumes when cts/drs# pin returns to a logic 0. the selection for cts# or dsr# is through mcr bit-2. 4.11.12 tfcnt[7:0] : transmit fifo level counter, read-only transmit fifo level byte count from 0x00 (zero) to 0x40 (64). this 8-bit register gives an indication of the number of characters in the transmit fifo. the fifo level byte count register is read only. the user can take advantage of the fifo level byte counter for faster data loading to the transmit fifo., which re- duces cpu bandwidth requirements. 4.11.13 txtrg [7:0]: transmit fifo trigger level, write only. an 8-bit value written to this register sets the tx fifo trigger level from 0x00 (zero) to 0x40 (64). the tx fifo trigger level generates an interrupt whenever the data level in the transmit fifo falls below this preset trigger level. 4.11.14 rfcnt[7:0]: receive fifo level counter, read only receive fifo level byte count from 0x00 (zero) to 0x40 (64). it gives an indication of the number of characters in the receive fifo. the fifo level byte count register is read only. the user can take advan- tage of the fifo level byte counter for faster data un- loading from the receiver fifo, which reduces cpu bandwidth requirements. 4.11.15 rxtrg[7:0]: receive fifo trigger level, write only an 8-bit value written to this register, sets the rx fifo trigger level from 0x00 (zero) to 0x40 (64). the rx fifo trigger level generates an interrupt whenev- er the receive fifo level rises to this preset trigger level. t able 15: uart reset conditions registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs spr bits 7-0 = 0xff fctr bits 7-0 = 0x00 efr bits 7-0 = 0x00 tfcnt bits 7-0 = 0x00 tftrg bits 7-0 = 0x00 rfcnt bits 7-0 = 0x00 rftrg bits 7-0 = 0x00 xchar bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx[ch-3:0] logic 1 irtx[ch-3:0] logic 0 rts#[ch-3:0] logic 1 dtr#[ch-3:0] logic 1
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 33 absolute maximum ratings power supply range 7 volts voltage at any pin -0.5 to 7v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw thermal resistance (10x10x1.4mm 64-tqfp) q -ja =70, q -jc =14 o c/w electrical characteriistics dc electrical characteristics ta = 0 o to 70 o c (-40 o to +85 o c for industrial grade package), vcc-3.3v and 5v +/-10% unless specified s ymbol p arameter 3.3v m in 3.3 max 5v m in 5v m ax u nits c ondition n otes v il input low voltage -0.3 0.7 -0.5 0.8 v v ih input high voltage 2.0 6.0 2.0 6.0 v v ol output low voltage 0.4 0.4 v iout=4 ma at 3.3v iout=6 ma at 5v v oh output high voltage 2.0 2.4 v iout=-1 ma at 3.3v iout=-2 at 5v i il input low leakage cur- rent -10 -10 ua i ih input high leakage cur- rent 10 10 ua x1 crystal/clock input low level -0.3 0.6 -0.5 0.6 v x1 crystal/clock input hign level 2.463.06 v c in input pin capacitance 55pf i cc power supply current 55ma external clock at 2mhz. a7-a0 at gnd, all inputs at vcc or gnd and out- puts unloaded i sleep sleep current 0.6 1.5 ma eight uarts asleep. a7- a0 at gnd, all inputs at vcc or gnd and out- puts unloaded. rin internal pull-up or pull- down resistance 3k15k3k15kohms
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 34 ac electrical characteristics ta = 0 o to 70 o c (-40 o to +85 o c for industrial grade package), vcc-3.3v and 5v +/-10% unless specified. s ymbol p arameter 3,3v m in 3.3v m ax 5v m in 5v m ax u nits n otes t c1, t c2 clock pulse period 10 8 ns t osc oscillator frequency 16 24 mhz t eck external clock frequency 33 50 mhz t as address setup (16 mode) 55ns t ah address hold (16 mode) 10 10 ns t cs chip select width (16 mode) 50 50 ns t dy delay between cs# active cycles (16 mode) 50 50 ns t rd read strobe width (16 mode) 50 50 ns t wr write strobe width (16 mode) 40 30 ns t rdv read data valid (16 mode) 35 25 ns t wds write data setup (16 mode) 15 10 ns t rdh read data hold (16 mode) 15 10 ns 70 pf test load t wdh write data hold (16 mode) 15 10 ns t ads address setup (68 mode) 10 5 ns t adh address hold (68 mode) 10 10 ns t rws r/w# setup to cs# (68 mode) 10 10 ns t rda read data access (68 mode) 35 25 ns t rdh read data hold (68 mode) 15 10 ns 70 pf test load t wds write data setup (68 mode) 10 10 ns t wdh write data hold (68 mode) 10 10 ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) 10 10 ns t csl cs# width (68 mode) 50 40 ns t csd cs# cycle delay (68 mode) 50 40 ns t 17d delay from iow# to modem output 50 50 ns t 18d delay to set interrupt from modem input 50 35 ns t 19d delay to reset interrupt from ior# 50 35 ns t rst reset pulse 40 40 ns
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 35 f igure 15. 16 m ode (i ntel ) d ata b us r ead and w rite t iming 16read t as t rdh t ah t rd t rdv t dy t rdh t rdv t ah t as t cs valid address valid address valid d ata valid d ata a0-a7 cs# io r# d0-d7 16 mode (intel) data bus read timing 16write t as t wdh t ah t wr t wds t dy t wdh t wds t ah t as t cs valid address valid address valid d ata valid d ata a0-a7 cs# io w # d0-d7 16 mode (intel) data bus w rite timing
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 36 68 mode (motorola) data bus read timing 68 mode (motorola) data bus write timing 68read t ads t rdh t adh t csl t rda t cs d t rws valid address valid address valid data a0-a7 cs# r/ w# d0- d7 t rwh 68write t ads t adh t csl t wds t cs d t rws valid address valid address valid data a0-a7 cs# r/ w# d0- d7 t rwh valid data valid data t wdh f igure 16. 68 m ode (m otorola ) d ata b us r ead and w rite t iming
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 37 f igure 17. m odem i nput /o utput p ort d elay io w # rts# dtr# cd# cts# dsr# int io r# ri# t 17d t 18d t 18d t 19d t 18d modem-1 active active change of state change of state active active active change of state change of state change of state active active f igure 18. t ransmit d ata i nterrupt at t rigger l evel stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 5 data bits 6 data bits 7 data bits start bit tx data next data start bit tx interrupt at transmit trigger level baud rate clock of 16x or 8x txnofifo-1 set at below trigger level clear at above trigger level
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 38 f igure 19. r eceive d ata r eady i nterrupt at t rigger l evel stop bit parity bit data bits (5-8) d0 d1 d2 d3 d4 d5 d6 d7 start bit rx data input first byte that reaches the trigger level rx data ready interrupt at receive trigger level rxfifo1 de-asserted at below trigger level asserted at above trigger level
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.1 39 package dimensions, 64-tqfp 48 33 32 17 116 49 64 d d 1 d d 1 b e a 2 a a 1 a seating plane l c note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.465 0.480 11.80 12.20 d 1 0.390 0.398 9.90 10.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. 1.0.2 40 revision history p1.0.0 preliminary 1.0.1 further clarification on a0-a7, rts#, cts#, dtr#, dsr# and enir pin description and throughout the datasheet, change v ih from 2.2v to 2.4v at 5v, change v oh from 2.4v to 2.0 at 3.3v and from 4v to 2.4v at 5v, change i cc from 10 to 5ma and its test condition to 2mhz. clock, and i sleep to 0.6 and 1.5ma for 3.3v and 5v respectively. revised the ac timing table. 1.0.2 updated values of ac electrical characteristics (t as , t ah , t cs , t rd , t ads , t adh , t wds , t wdh ). added exars uart technical support e-mail address to first and last page.
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart rev. 1.0.2 41 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2001 exar corporation datasheet december 2001 send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.
XR16L784 ? ? ? ? high performance 5v and 3.3v quad uart rev. p1.0.2 preliminary i table of contents general description ............................................................................................... 1 a pplications .............................................................................................................................. ............. 1 new f eatures .............................................................................................................................. ......... 1 figure 1. block diagram ....................................................................................................... ................ 1 figure 2. pin out assignment .................................................................................................. ............ 2 ordering information ............................................................................................................................ 2 pin descriptions ....................................................................................................... 3 description .................................................................................................................. 6 1.0 XR16L784 registers ....................................................................................................... .................. 6 figure 3. the XR16L784 registers mapping ...................................................................................... . 6 1.1 device configuration register set .......................................................................................... 6 t able 1: XR16L784 r egister s ets ....................................................................................................... 7 t able 2: d evice c onfiguration r egisters .......................................................................................... 7 1.1.1 the global interrupt source registers ................................................................................... .. 8 int0 channel interrupt indicator: ............................................................................................ .......................... 8 int1 and int2 interrupt source locator ....................................................................................... .................... 8 figure 4. the global interrupt registers, int0, int1, int2 and int3 ............................................... 8 t able 3: uart c hannel [3:0] i nterrupt s ource e ncoding and c learing ....................................... 9 1.1.2 general purpose 16-bit timer/counter. [timermsb, timelsb, timer, timecntl] (default 0xxx-xx-00-00) ................................................................................................................ ................ 9 figure 5. timer/counter circuit. .............................................................................................. ............. 9 t able 4: timer control r egister ................................................................................................. 10 1.1.3 8xmode [7:0] (default 0x00) ............................................................................................ .... 11 1.1.4 rega [7:0] is reserved (default 0x00) .................................................................................. 11 1.1.5 reset [7:0] (default 0x00) .............................................................................................. ...... 11 1.1.6 sleep [7:0] .....................................................................................................(default 0x00) 11 1.1.7 device identification and revision ...................................................................................... ... 11 1.1.8 regb [7:0] ......................................................................................................(default 0x00) 12 2.0 crystal oscillator / buffer ............................................................................................... ..... 12 3.0 transmit and receive data ................................................................................................. ....... 12 3.1 fifo data loading and unloading through the uart channel registers, thr and rhr. ..... 12 figure 6. typical oscillator connections ...................................................................................... ..... 12 t able 5: t ransmit and r eceive d ata r egister , 16c550 compatible .............................................. 13 4.0 uart ...................................................................................................................... ............................... 13 4.1 p rogrammable b aud r ate g enerator .................................................................................................................. 13 figure 7. baud rate generator ................................................................................................. .......... 13 t able 6: t ypical data rates with a 14.7456 mh z crystal or external clock at 16x s ampling . 14 4.2 a utomatic rts/dtr h ardware f low c ontrol o peration .................................................................................. 14 4.2.1 automatic cts/dsr hardware flow control operation ........................................................ 14 figure 8. auto rts/dtr and cts/dsr flow control operation ..................................................... 15 4.3 i nfrared m ode .............................................................................................................................. ........................... 15 figure 9. infrared transmit data encoding and receive data decoding ....................................... 16 4.4 i nternal l oopback .............................................................................................................................. .................... 16 figure 10. internal loop back ................................................................................................. ........... 17 4.5 uart channel configuration registers and address decoding. ................................................. 17 t able 7: uart channel configuration registers. ............................................................. 18 t able 8: uart channel configuration registers description. s haded bits are enabled by efr b it -4. ........................................................................................................................ 19 4.6 t ransmitter .............................................................................................................................. ............................... 20 4.6.1 transmit holding register (thr) ......................................................................................... .. 20 4.6.2 transmitter operation in non-fifo ....................................................................................... . 20 figure 11. transmitter operation in non-fifo mode ....................................................................... 20 4.6.3 transmitter operation in fifo ........................................................................................... .... 20
? ? ? ? XR16L784 high performance 5v and 3.3v quad uart preliminary rev. p1.0.2 ii 4.6.4 auto rs485 operation .................................................................................................... ...... 20 figure 12. transmiitter operation in fifo and flow control mode ............................................... 21 4.7 r eceiver .............................................................................................................................. .................................... 21 4.8 r egisters .............................................................................................................................. ................................... 21 4.8.1 receive holding register (rhr) .......................................................................................... . 21 4.8.2 baud rate generator divisors (dll and dlm) ..................................................................... 21 figure 13. receiver operation in non-fifo mode ............................................................................ 22 figure 14. receiver operation in fifo and flow control mode ..................................................... 22 4.8.3 interrupt enable register (ier) ......................................................................................... .... 22 4.9 ier versus r eceive fifo i nterrupt m ode o peration ......................................................................................... 22 4.10 ier versus r eceive /t ransmit fifo p olled m ode o peration ............................................................................ 23 4.11 i nterrupt s tatus r egister (isr) ........................................................................................................................ . 23 4.11.1 interrupt generation: .................................................................................................. ......... 23 4.11.2 interrupt clearing: .................................................................................................... ............ 24 t able 9: i nterrupt s ource and p riority l evel ............................................................................... 24 4.11.3 fifo control register (fcr) ............................................................................................ ... 24 t able 10: t ransmit and r eceive fifo t rigger l evel s election .................................................... 25 4.11.4 line control register (lcr) ............................................................................................ .... 25 4.11.5 modem control register (mcr) or general purpose outputs control. .............................. 26 t able 11: p arity selection ................................................................................................................ 26 4.11.6 line status register (lsr) ............................................................................................. ..... 27 4.11.7 modem status register (msr) - read only ....................................................................... 28 4.11.8 modem status register (msr) - write only ........................................................................ 28 t able 12: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive ........ 29 4.11.9 scratch pad register (spr) ..................................................................................... 29 4.11.10 feature control register (fctr) ....................................................................... 29 t able 13: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected ....................... 29 4.11.11 enhanced feature register (efr) .................................................................................... 30 t able 14: s oftware f low c ontrol f unctions ................................................................................ 31 efr[6]: a uto rts or dtr f low c ontrol e nable ............................................................................ 31 4.11.12 tfcnt[7:0] : transmit fifo level counter, read-only ..................................................... 32 4.11.13 txtrg [7:0]: transmit fifo trigger level, write only. ..................................................... 32 4.11.14 rfcnt[7:0]: receive fifo level counter, read only ....................................................... 32 4.11.15 rxtrg[7:0]: receive fifo trigger level, write only ........................................................ 32 t able 15: uart reset conditions .............................................................................................. 32 absolute maximum ratings ................................................................................ 33 electrical characteriistics ............................................................................. 33 dc electrical characteristics ............................................................................................... 3 3 ac electrical characteristics ............................................................................................... 3 4 figure 15. 16 mode (intel) data bus read and write timing .......................................................... 35 figure 16. 68 mode (motorola) data bus read and write timing ................................................... 36 figure 17. modem input/output port delay ...................................................................................... 37 figure 18. transmit data interrupt at trigger level ......................................................................... 3 7 figure 19. receive data ready interrupt at trigger level .............................................................. 38 package dimensions, 64-tqfp ............................................................................. 39 r evision h istory .............................................................................................................................. .... 40 table of contents .................................................................................................... i

▲Up To Search▲

Price & Availability of XR16L784

	To Download XR16L784 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .